stk15c88 256-kbit (32 k 8) powerstore nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-50593 rev. *c revised april 10, 2011 256-kbit (32 k 8) powerstore nvsram features 25 ns and 45 ns access times pin compatible with industry standard srams automatic nonvolatile store on power loss nonvolatile store under software control automatic recall to sram on power up unlimited read/write endurance unlimited recall cycles 1,000,000 store cycles 100 year data retention single 5 v + 10% power supply commercial and industrial temperatures 28-pin (300 mil and 330 mil) soic packages rohs compliance functional description the cypress stk15c88 is a 256kb fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap ? technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. powerstore nvsram products depend on the intrinsic system capacitance to maintain system power long enough for an automatic store on power loss. if the power ramp from 5 volts to 3.6 volts is faster than 10 ms, consider our 14c88 or 16c88 for more reliable operation. logic block diagram [+] feedback not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *c page 2 of 17 contents pin configurations ........................................................... 3 device operation .............................................................. 4 sram read ....................................................................... 4 sram write ....................................................................... 4 autostore operation ........................................................ 4 hardware recall (power up) ........................................ 4 software store ............................................................... 4 software recall ............................................................. 4 hardware protect .............................................................. 5 noise considerations ....................................................... 5 low average active power .............................................. 5 best practices ................................................................... 5 maximum ratings ............................................................. 7 dc electrical characteristics .......................................... 7 data retention and endurance ....................................... 8 capacitance ...................................................................... 8 thermal resistance .......................................................... 8 ac test conditions .......................................................... 8 ac switching characteristics ... ...................................... 9 sram read cycle ............................................................. 9 switching waveforms ...................................................... 9 sram write cycle .......................................................... 10 switching waveforms .................................................... 10 autostore or power up recall .................................. 11 switching waveforms .................................................... 11 software controlled store/recall cycle ................ 12 ordering information ...................................................... 13 ordering code definitons ...... .................................... 13 package diagrams .......................................................... 14 document history page ................................................. 16 sales, solutions and legal information ....................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17 [+] feedback not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *c page 3 of 17 pin configurations figure 1. pin diagram - 28-pin soic table 1. pin defini tions - 28-pin soic pin name alt i/o type description a 0 ?a 14 input address inputs. used to select one of the 32,768 bytes of the nvsram. dq 0 -dq 7 input or output bidirectional data i/o lines . used as input or output lines depending on operation. we w input write enable input, active low . when the chip is enabled and we is low, data on the i/o pins is written to th e specific address location. ce e input chip enable input, active low . when low, selects the chip . when high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . $ $ $ $ ' 4 ' 4 ' 4 $ $ $ $ $ $ $ $ ' 4 ' 4 9 6 6 $ & |